High-voltage devices are used as the core components of semiconductor devices for automobiles, or as the core components of semiconductor devices for networks or the driving of displays. As an example, among high-voltage devices, a 15 Volt (V) bidirectional high-voltage device is integrated with a low-voltage device in the same chip, and is chiefly used at the output stage of the data driver Integrated Circuit (IC) of a Liquid Crystal Display (LCD) or an Organic Light Emitting Diode (OLED) display.
In particular, the data driver IC for a display is configured such that a single output unit includes a minimum of 240 terminals and a maximum of 640 terminals, so that the uniformity of these output terminals directly affects the uniformity of image quality of a display. Accordingly, it is very important to insure that the output terminals of the data drive IC have uniform electrical characteristics.
FIG. 1 is a sectional view of a conventional high-voltage device, in accordance with the prior art.
The high-voltage device 10 shown in FIG. 1 is an NMOS transistor. The NMOS transistor 14 is formed in a P-type well 18 formed in a substrate 12, and includes a source and a drain, which are formed in respective N-type drift regions 20 and 22, and a gate 26, which is disposed on a gate insulating layer 24. Spacers 27 are formed on respective sidewalls of the gate 26. The NMOS transistor 14 is electrically connected to the outside via a source electrode 32, a gate electrode 30 and a drain electrode 34 that are insulated from each other by an interlayer insulating layer 36.
A conventional process of manufacturing the high-voltage NMOS device 10 is described below, according to the prior art (refer to a flowchart shown in dotted lines in the right portion of FIG. 3). At Event 200, a wafer is prepared, at Event 202, a mask pattern for forming a High-Voltage (HV) well 18 is formed on a substrate 12, and, at Event 204, P-type dopants are ion-implanted into the substrate. The ion-implanted dopants are diffused into the substrate, and a high-voltage P-type well 18 is formed, at Event 206, through a high-temperature (for example, 1200° C.) drive-in process to increase the breakdown voltage of the semiconductor device. Thereafter, the mask pattern is removed, at Event 208, another mask pattern for forming the drift regions 20 and 22 is formed, at Event 210, N-type dopants are ion-implanted into the substrate using the pattern, and, at Event 212, the N-type drift regions 20 and 22 are formed in the high-voltage P-type well 18 through a high-temperature (for example, 1150° C.) drive-in process to increase breakdown voltage.
The well region 18 and the drift regions 20 and 22 are formed through the above-described processes to form the high-voltage NMOS device 10 and, thereafter, a process of manufacturing a low-voltage device in the same wafer is performed. That is, at Event 214, device isolation oxide layers are formed in the substrate 12 through, for example, a Local Oxidation of Silicon (LOCOS) process, at Event 216, a Low-Voltage (LV) well pattern is formed, and, at Event 218, the low-voltage well (not shown in FIG. 1) is formed by performing ion implantation into the substrate using the pattern. Thereafter, at Event 220, a Rapid Thermal Process (RTP) or an annealing process is performed to cure the substrate, which was damaged by the ion implantation (for example, to compensate for stress to which the substrate was subjected, and uniformly align the crystalline structure of the substrate).
In order to form the conventional high-voltage NMOS device 10, two photolithography processes and two high-temperature drive-in processes are required to form the high-voltage well 18 and the drift regions 20 and 22. Accordingly, in order to form a high-voltage NMOS device and a high-voltage PMOS device on a single substrate, for example, using a 0.35 μm CMOS process, a total of four photolithography processes and a plurality of high-temperature drive-in processes are required.